? semiconductor components industries, llc, 2000 october, 2000 rev. 3 1 publication order number: mc10el51/d mc10el51, mc100el51 5vecl differential clock d flipflop the mc10el/100el51 is a differential clock d flip-flop with reset. the device is functionally similar to the e151 device with higher performance capabilities. with propagation delays and output transition times significantly faster than the e151 the el51 is ideally suited for those applications which require the ultimate in ac performance. the reset input is an asynchronous, level triggered signal. data enters the master portion of the flip-flop when the clock is low and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. the differential clock inputs of the el51 allow the device to be used as a negative edge triggered flip-flop. the differential input employs clamp circuitry to maintain stability under open input (pulled down to v ee ) conditions. the 100 series contains temperature compensation. ? 475 ps propagation delay ? 2.8 ghz toggle frequency ? esd protection: > 1 kv hbm, > 100 v mm ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors on d, r, and clk ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 73 devices http://onsemi.com device package shipping ordering information mc10el51d so8 98 units/rail mc10el51dr2 so8 2500 tape & reel mc100el51d so8 98 units/rail mc100el51dr2 so8 2500 tape & reel mc10el51dt tssop8 98 units/rail mc10el51dtr2 tssop8 2500 tape & reel mc100el51dt tssop8 98 units/rail mc100el51dtr2 tssop8 2500 tape & reel l = wafer lot y = year w = work week *for additional information, see application note and8002/d h = mc10 k = mc100 a = assembly location so8 d suffix case 751 marking diagrams* tssop8 dt suffix case 948r 1 8 1 8 alyw kel51 1 8 hel51 1 8 alyw alyw hl51 1 8 alyw kl51 1 8
mc10el51, mc100el51 http://onsemi.com 2 1 2 3 45 6 7 8 q v ee v cc logic diagram and pinout assignment d q clk clk r d r truth table d* l h x r* l l h clk* z z x q** l h l z = low to high transition pin function r ecl reset input d ecl data input clk, clk ecl clock inputs q, q ecl data outputs v cc positive supply v ee negative supply pin description * pin will default low when left open. **pin will default low when inputs are left open. maximum ratings (note 1.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w q jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 5% c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc10el51, mc100el51 http://onsemi.com 3 10el series pecl dc characteristics v cc = 5.0 v; v ee = 0.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 24 29 24 29 24 29 ma v oh output high voltage (note 2.) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2.) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (single ended) 3770 4110 3870 4190 3940 4280 mv v il input low voltage (single ended) 3050 3500 3050 3520 3050 3555 mv v ihcmr input high voltage common mode range (differential) (note 3.) 2.5 4.6 2.5 4.6 2.5 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.3 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.25 v / 0.5 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v. 10el series necl dc characteristics v cc = 0.0 v; v ee = 5.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 24 29 24 29 24 29 ma v oh output high voltage (note 2.) 1080 990 890 980 895 810 910 815 720 mv v ol output low voltage (note 2.) 1950 1800 1650 1950 1790 1630 1950 1773 1595 mv v ih input high voltage (single ended) 1230 890 1130 810 1060 720 mv v il input low voltage (single ended) 1950 1500 1950 1480 1950 1445 mv v ihcmr input high voltage common mode range (differential) (note 3.) 2.5 0.4 2.5 0.4 2.5 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.3 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.25 v / 0.5 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v.
mc10el51, mc100el51 http://onsemi.com 4 100el series pecl dc characteristics v cc = 5.0 v; v ee = 0.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 24 29 24 29 30 36 ma v oh output high voltage (note 2.) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mv v ol output low voltage (note 2.) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mv v ih input high voltage (single ended) 3835 4120 3835 4120 3835 4120 mv v il input low voltage (single ended) 3190 3525 3190 3525 3190 3525 mv v ihcmr input high voltage common mode range (differential) (note 3.) 2.5 4.6 2.5 4.6 2.5 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / 0.5 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v. 100el series necl dc characteristics v cc = 0.0 v; v ee = 5.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 24 29 24 29 30 36 ma v oh output high voltage (note 2.) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2.) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv v ihcmr input high voltage common mode range (differential) (note 3.) 2.5 0.4 2.5 0.4 2.5 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / 0.5 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v.
mc10el51, mc100el51 http://onsemi.com 5 ac characteristics v cc = 5.0 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 5.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 1.8 2.8 2.2 2.8 2.2 2.8 ghz t plh t phl propagation delay to output clk r 325 305 465 455 605 605 385 355 475 465 565 565 440 410 530 510 620 620 ps t s setup time 150 0 150 0 150 0 ps t h hold time 250 100 250 100 250 100 ps t rr reset recovery 400 200 400 200 400 200 ps t pw minimum pulse width clk, reset 400 400 400 ps v pp input swing (note 2.) 150 1000 150 1000 150 1000 mv t jitter cycletocycle jitter tbd tbd tbd ps t r t f output rise/fall times q (20% 80%) 100 225 350 100 225 350 100 225 350 ps 1. 10 series: v ee can vary +0.25 v / 0.5 v. 100 series: v ee can vary +0.8 v / 0.5 v. 2. v pp( min) is minimum input swing for which ac parameters guaranteed. the device has a dc gain of 40. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10el51, mc100el51 http://onsemi.com 6 package dimensions so8 d suffix plastic soic package case 75107 issue v seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m tssop8 dt suffix plastic tssop package case 948r02 issue a dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016
mc10el51, mc100el51 http://onsemi.com 7 notes
mc10el51, mc100el51 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10el51/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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